1. Field of the Invention
The present invention relates to a semiconductor device which is prevented from breaking down due to a surge voltage such as electrostatic discharge (hereinafter, referred to as ESD).
2. Description of the Related Art
In one example, a conventional semiconductor device having the following structure is known. FIG. 10 is a cross-sectional view illustrating the conventional semiconductor device.
As shown in FIG. 10, an N type epitaxial layer 163 is formed on a P type semiconductor substrate 162. A diffused resistor 161 is formed in the epitaxial layer 163. A P type diffusion layer 164 is formed in the epitaxial layer 163, and P type diffusion layers 165, 166 are formed to overlap the P type diffusion layer 164. A high potential (VH) such as a power supply potential (Vcc) is applied to the P type diffusion layer 165, while a low potential (VL) such as a ground potential is applied to the P type diffusion layer 166.
In addition, a P type diffusion layer 168 and an N type diffusion layer 169 are formed in the epitaxial layer 163 at a portion along the inner circumference of an isolation region 167. The P type diffusion layer 168 and the N type diffusion layer 169 form a PN junction region 170. The N type diffusion layer 169 partly overlaps a P type diffusion layer 171 of the isolation region 167. The PN junction region 170 has a junction breakdown voltage lower than that of a PN junction region 172 of the diffused resistor 161. When a surge voltage such as an ESD surge is applied to the diffused resistor 161, the PN junction region 170 breaks down prior to the PN junction region 172 and thereby the diffused resistor 161 is protected. An on-current I8 generated in a parasitic transistor Tr (hereinafter, may be referred to as a parasitic Tr) flows into the substrate 162 through the isolation region 167. This technology is described for instance in Japanese Patent Application Publication No. 2007-317869 (pp. 6-8, FIG. 1).
As described above, in the conventional semiconductor device, when a surge voltage such as an ESD surge is applied to the diffused resistor 161, the PN junction region 170 breaks down prior to the PN junction region 172, and then the on-current I8 of the parasitic Tr is generated. A protection element including the P type diffusion layers 168, 171 and the N type diffusion layer 169 is formed in a surface portion of the epitaxial layer 163, and hence the on-current I8 of the parasitic Tr flows into the substrate 162 through the surface portion of the epitaxial layer 163. Here, an insulating layer having a thermal conductivity lower than that of silicon is stacked on formation regions of the P type diffusion layers 168, 171 and the N type diffusion layer 169, and hence the surface portion of the epitaxial layer 163 has poor heat dissipation. The on-current I8 of the parasitic Tr is so large that the heat caused by the on-current I8 of the parasitic Tr may lead to thermal breakdown of the surface portion of the epitaxial layer 163 (the formation region of the P type diffusion layers 168, 171 and the N type diffusion layer 169).